Pulse-operated receiver

ABSTRACT

Disclosed is a receiver for a navigation system of the Omega type which operates with pulse-modulated signals. The phase of received and local signals is compared by quantized pulses; phase equalization, commutating gate control, phase tracking, and synchronization of gate patterns with time-sequence input signals are obtained by pulse insertion into, or deletion from, signal loops which contain phase detecting, sequential signal selecting, and readout control components. Phase coincidence is counted cumulatively and is electromechanically stored. Lane position is recorded by pulse insertion. Components are constructed and interrelated to reduce noise and improve selectivity to enhance the benefits obtained by pulsed operation control.

United States Patent 1191' Orlanis PULSE-OPERATED RECEIVER inventor:Charles E. Odams, Londonderry. NH.

[73] Assignee: American Standard Inc., New York,

. Filed: Dec. 31, 1969 'Appl. No; 889,363

I 343/102 TC, 102 Fr I00 1 References Cited UNITED STATES PATENTS3.465.340 9/1969 OBrien et al. 343/l05 3.47l,856 l0/l969 Laughlin ct ll.343/l05 R 3.623.!00 11/197:

Rapp 343/l05 R us. Cl. 343/105 LS, 343/105 R. 343/112 0 51 in: CI

V [581 min oi Search .4 343/105 LS; 105 R. 102 c.

[.ll] 3,818,477 June 18, 1974 Primary ExaminerCarl D. QuarforthAssistant Examiner-l M. Potenza Attorney, Agent, or Firm-JeffersonEhrlich; Robert G Crooks v ABSTRACT Disclosed is a receiver for anavigation system of the Omega type which operates with pulse-modulatedsignals. The phase of received and local signals is compared byquantized pulses; phase equalization, cummutating gate control, phasetrucking. amd synchronization of gate patterns with timc-sequencc inputsignails are obtained by pulse insertion into, or dclction from, signalloops which containphase detecting sequential signal selecting. andreadout control componentsv Phase coincidence. is counted cumulativelyand is electromechanically stored. Lime position is restructed andinterrelated to reduce noise and improve selectivity to enhance thebenefits obtained by pulsed operation control.

34 Qlaims, 19 Drawing Figures l 0701? 1mm mm m i I out? 1mm W1 l I 2840.ma a/szc i 1'29 //4 m2 H;

J g 2040, 198 h was PAIENIEDJIIIWW E? had? 12 Pmmmu I sum sum 070F12UNDNQ min 1% on M Pmmwmaw" sum as or 1;,

. l PULSE-OPERATED RECEIVER BACKGROUND OF THE INVENTION l. Field of theInvention The invention relates to radiowave communicationsystems'7(Class 343). and particularly to transmitting beacons of theisophase type producing positiondetcrminative signals (Subclass I05).

,2. Description of the Prior Art The rapid increase in volume and speedof long distance ship and airplane traffic has increased the requirement for a reliable worldwide navigational system.

quencies and based on phase-comparison technology are particularlyuseful. Several variations of such systemshave been investigated.Installations which furnish hyperbolic lines of position defined byphase differences oftime-shared signals'from several transmittinglocations are preferred. The reliability and phase stability of VLFpropagation makes possible the use of verylong-range. accurate,positiondetermining signals for establishing a hyperbolic line 'systemwherein position is defined by the points of phase coincidence oi a pairof signals received respectively from each of at least tftwo preciselysynchronized transmitters. The hyperbolic lines of position are plotted.for instance. on a navigation chart. to produce grid lines. and theselines I .are separated by lanes whose width depends on the vyave lengthof the transmitted signal. Phase coincidences of a synchronized. wavegenerator on the ambulating craft whose position is to be determinedwith the signals producing the grid lines traversed by the craft"furnish a fix and course trace. In order to obtain a fix. s gnals' mustbe received and. processed from at least three transmitting stations.One system of the typede- 'ribed is the OMEGA Navigation System. TheOmega system and other similar systems are described in the l iliterature. for examplepin "Selected Papers Related to Long-Range RadioNavigation" presented at the (ongross on Long-Range Navigation held .inMunich. Germany.- during 26-31 Aug. 1965 and reprinted by the OmegaImplementation Committee. for the United States Navy Department. US.patents classified. as in tlicatcd above. also deal with this subjectmatter. for we ample. US. Pat Nos. v 2.77it JH3. 3.20%356, 3.26323! and.3.383.397.

All receivers presently used in these. navigation systerns are known mhave limitations affecting their use.

They are biilky.-v and they are difficult to operate therebynecessitating theuse of skilledtrzunrrrl ncrsmr m l; Additionally.lhe'reccivcrsaru inaccurate rind are not asrehabh: as they need to be inthis application 'l-hey are tix'icruiivc and are not suimblr l'ur smut-ziu tomwlic or automatic operation. thu tin-y an: out

SUMMARY OF THE INVENTION It is. therefore. an object of the invention toprovide an improved navigation system receiver.

5 An additional object is to providea navigation system receiver capableof fixing the positionol' a craft with a high degree of accuracy.

Another object is to provide a'more accurate navigation system receiverthrough the use of pulsemodulation techniques and circuitry.

Still another object is to provide a more accurate navigation systemreceiver through the use of pulsequantizing techniques and circuitry formaking phasedifference measurements.

A further object is to provide a navigation system rcceiver which has ahigh degrce'of selectivity and low noise. v v

A still further object is to provide a navigation system receiver havingan improved meansfor displaying the position of the craft.

Another object is' to provide'means for displaying receiver informationin a more reliable manner.

Still another object is to provide means t'or preserving the displayednavigation data in the event of a power failure. I

A further object is to provide a navigational receiver which has asimplified design suitable for modular construction and easeofmaintenance.

A still further object is to provide a navigational re ceiver which ischaracterized by the ease with which navigation is accomplished throughthe use thereof.

In the embodiment described. the invention is characterized by the useof pulsesignal or digital circuitry wherever possible. forintercircuitry signal-trains as well as output signals".- the circuitryfunctions being defined in terms of pulse insertion and deletion. ofpulse amplitude. duration and position modulation. or pulse quantizing.of pulse multiplexing and of counting and acleristic concept is applied.directly. or indirectly. for its ultimatcpurpose. to various componentsof the navigational system. which comprises A local reference oscillatorl a phase error detector. a selector for separate comparison of'the several received time-shared signals with the local timereference. circuitry for muuiingthe local phase with the phases ofselected. rcccivd sig mils. and tracking apparatus for translating phasedifferences into terms ol the hypcrholicfgrid.

More particularly. the aforesaid embodiment in a principal aspect oitheinvention invohcs primary phase equalization of local timing signals andincoming i'navigationzil signals by means oi pulse insertion. controlledbypiilscs ot' opposite poiarity which originatiin a phaseLlfOr'l'lClCtlUl.

In another aspect. the signals coming from the sc ccivcr by commutatorgates which are timed withthc m incoming ignals by pulse insertion ordeletion signals A'l uither aspect deals with cou'ilnncil performance oithe abovementioned primary phase you-titration .is well an rgitr liming:operations in lltttllil i l pirilstkug llfll 3 v I g Aloui'tli aspectltritiumnod-Willi rtuinilzunc. tll titnl l'nunliii f til lllt naught.hildzitli ilrr'tlui'lcti IILI thi: lltiic m phm ttjil storing ot"informalion-carrying. pulse trains. This charis related tothe principalaspect of phase no. to isa detailed circuit re: comparatorandcoildrivcfiH PK 1 1 is a detailed circuit diagram of the lane position recordinggroup. frame D;-and

equalization involving pulle-insertion techniques. nos. 12, is, u, isand 16 are detailed circuit unln the-seventh of the"above-mentioned lanegrams of the amplifier group frameI-T: position recording isaccomplished by pulse insertion v l r y m i d according) h rin ipalaspect. DESCRIPTION OF PREFERRED EMBODIMENT 'An "additional aspectdeals, in connection with the y A l a above features. with amplificationby 'way of distributed to Geneml outline a g filters. l y With referenceto FIGS. 1 and la, an operational description of the system as a wholewith some simplifica- RIEF ESC PTION OF THE DRAWINGS r A D trons, willfirst be presented inthe form of a tabulation a 111 t h i dliigfamswhiQh which combines references to the ft'mction blocksof s hs uw atabulation. f F the descnpnon FIG. 1 with their operations correlation.The blocks are r pg to he e gu s. illustrats s n r identified byidentical numerals inboth the tabulation .strucmre and operation ofthe-present system n easily and in FIGS. 1 and 1.1 I f mt s bl -f i x yl i As mentioned above.' four transmitters, with their re- .1 i Pblfllikldlagmm of Q F spective signals phase-synchronized, are assumedfor system mp gv a5 d from F LF E Y purposes of the present description.The signals from a l? than functlmlal interrelation; h Identifytherespective transmitters are indicated in FIG. I at sn s of the blockscorrespond to those of FIG 108, it. 10c and 10d. As indicated. eachtransmitter i' p of blocks in doncd l l mcortransmits for a given periodof time, a, b, c, d, and the 8b0v -Char Inventive aspects transmittingperiods of each. transmitter is staggered marltcd'with capital letters;'5 23 with respect to all other transmitters; FIG. 1a schematiand 5arr-detailed ifil'cuii dlagrams f the cally represents two hyperboliclane systems estabeq aliza i n gl' P. within dotted line. frame A;lished by transmitted signal pairs, such as a, b and c, d, l the wiringof the detail circuitry of this group and of the respectively. andformirig,' when superimposed, a v other groups is completely evidentfrom the respective nearly rectilinear grid. While F K]. 1a shows theplotted figures, and their description is completed by a tabula- 3signals from the fourt'ransrnitters 10a, 10b. 10c. 10d tion referring tothe'numbers marked on these figures and their hyperbola axes, it will beunderstood that the giving the names. ratings. or other identificationsspatial relation of transmitters and grid is grossly disof the circuitelements; toned, as indicated by the broken axis lines. it should FIGS.6, 6A, 6B and. 7 are detailed circuit diagrams be noted that FIG. 1and-the tabulation set forth in the ofthe s g al segregation group,frarne B; following material include only the components neces- FlG8isadetailed circuitdiagram of the cumulative sary to process the signalfrom one transmitter. alcounting group, frame C; though the number ofcomponents required for pro- FIG. 9 is a timing diagram illustrating theoperation cessing all the signals; in a complete system, as deof thestorage and count-out circuitry. group C; scribed. is indicated bylegend.

Input Output Mark Name from Operation to 1 I00 Plurality Transmitsynchronized \"LF ([02 KC) signals in l 10b (here four) timed sequencefor corresponding receiver 1 10c of transchannels 7 l l I miners lllAntenna and I I0 Receiving antenna: for 10.2 KC signal, and l lZaCoupler 4.54211 coupling with amplifier l l2a RF l l 1 Distributedfilter and limiter amplifier with 1 12b Amplifier optimalphasc"'ccnstancy. I121; IF I l2a Supcrhetcmdyne amplifier furnishingsinus0|- l|6 Amplifier I Mr dal (r8 KC signal 123 l 14 Reference l2)Generates stable pulse tram continuous at 1 l2 Oscillator 20M) KC. foramplifier. timing-function 2 M; with Local generator and addersuhtractors. Feeds into 1 l5 local synthesizer 3 Ida which supplier. 17KC 1 i9 signal after division by I20 122 l 128 l l 5 Timing Fune- I22Generates commulation pattern for segregating l 18': tion Genera timedsequence signals a. h. c. d in timed l Blip tor sequence Patternsynchronized with pall3! terns of a. b. r. d l1.

m Y t y I32 H6 Phase Error 1 12 i Compares signuls a. lift 4withlucalsquarc I If? I Detector |2l waves from trunking synthesizers 20Fur nialicai l) C. voltage go ng from U,.' to -05 vults as phase errorgoes frnni to +90 I I7 Mum! l H1 .Analngdigiuil Comm-Ht! ul 0 phaseerror I Ito: Pulse signal into pulses in corresponding [risque n l Hipcivil mm mm pm for 7cm will in in my; for it Q vnll Pulse cmrcspnndmgtiii and will uh corresponding i and burnt, il|'\L -t ,l p and n llllp Shimnter l H Erpvvpnlc (our tun-limp lmvjvlm \lu mm 1 W llln' Fm." pair I l!mnrmh u. b r I, l mu ul timing pawl- 11 to display synchronizationpattern in dual trace against same time base Input u put Mart Nome fromOperation to Illa (matter from It!) sndplndnsignsls Irom'll7. Open I262Ilp channel) slightly shorter thsn e. b. c. d sequences etc. H9 1Adder- H4 Combine p. n pulses from I! and "Up. llBn I20 2l9' SuhtnctorsI lip with continuous pulse train 2040 KC from I I4. 3I9 ,Four(one llllninserting or cnnceling at 2040 KC pulse for H9 r channel) es'ch p. npulse respectively I20 radio; I I9 Frequency dividers counting down by nlactor I2] 220 Synthesizers of 300. Furnish 0.8 KC uurc waves with I29320 Four( one phases advanced 1/300 a cycle for each I30 .420 perchannel) pulse added and retarded l/300 for each pulse deleted.Continuous 6.8 KC output signal. Once phase lock with III isestablished. I I7 ceases to furnish p. n pulses The pulses fed from M7to I25. I26. measure the phase lead or lag of the signals from l0.quantized at H300 cycle I2l Four long I20 Close the tracking servo loo 5I9. back to I I6 Gates ll6. Driven by ll8p. ll8n rom llS. synchroniledwith a. b. c. d. Open for full 0. b. c. y d I22 Sequential I I4: Causespulses from I24 to be added or deleted I 15 Channel I I4 untilcoincidence is reached between gate Snychroniz- I 24 pattern of I I5 anda. b. c. d envelopes from in; Circuit I24 as observed at I33 when I24ismanually sto d 7 I24 Pipe Maeiiriilly controlled. furnishes pulses to beI Generator added or subtracted at I22 I22 I25 Add Counter 1 l lBp Sumadd pulses from ll8p of one channel with I27 Stores I I8! subtractpulses from 2I8n of another channel.

- I Feed into comparator and coil driver I27 I26 Subtract l I8p Sumsubtract pulses from l l8n of one channel I27 Counter lI8n with addpulses from ll8p of another channel. i j Stores .1 Feed into coils l26.l

' I27 Comparaton I25 Prevents counter from being driven in'both I275Coil Driver I26 directions simultaneously I275 Counters I27Electromcchanically record continuously the OUTPUT net differenceprovided by I27. this being the change of one centilane I28 SynthesizerI14 Develops 6.8 KC for I29 I29- I23 I29 Loop Digital I20 Detects phasedifference between I I4 and one I I4 I Phase preferred (usually thestrongest received) Detector loop of I20 (one of a. b. r. d). to lock II4 to respective sender. in digital terms I30 Display I20 Compare 6.8 KCoutput signals of pairs I9. 20. I3] Phase Furnish-ramps from zero tomaximum correspond- Detectors ing to phase differences from zero to full1 cycle I3l Chart I30 Graphically record the lanes crossings as OUTRUTRecorders lines traversing the chart relatively to a f time base I32Envelope I I2!) Develops envelopes of a. h. t. d I3l a Detector I28 v 7I33 "Envelope I I5 Presents a. b, c. d envelopes and commutation OUTPUTScope I32 structure. subdivision headings have been arranged to identifythe previously mentioned framcs". marked Witkcapital letters in FIG. 2.Respective blocks of the Schematic Drawings and frames are marked withno merals which correspondingly recur in all figures.

Where it is appropriate to the description. interconbetween the variouscomponents are marked with labels coded to indicate the blocks by theirrespective numerals and are further labeled by i for input and a lowoutput. respectively. for example. i H2 is the input temiimtl from blockI12. and 0 III is the output terminal to block I12.

A. Hlasrlncltcd Loops Referring in F303. 3.

4 and 5 which discloses a phase-locked loop. frame A. including blockssuch as H6, I17, "9 and 120, and refer additionally to FIGS. I and 2 inorderto correlate the description to the systcm operation. Eachtransmitted signal from stations I00. 10b. we and "Id is tracked in arespective servo loop which is adapted to develop a continuous localsignal which is phase-locked to the intermitten transmitted signal. Forinstance, a single reference oscillator I14 (FIG. 2) provides a local.precision. phase: signal for all servo loops. Each respective loopincludes a common; phase-error detector II6 which compares the signalfrom mixer I l2b with a corrected. local signal derived from referencetmcillntor H ll The phase error detector III: has a DC output which ispositive. negative. or zero depending on the phase dillerence bctweenthe compared tignuls. This 01'? output is fed to and cot'ttrols abilateral pulse generator II? which is common to each loop bu. hm. twooutput lines. one line carrying pulses corresponding to apositiveiphase'dif ference. theother line carrying pulses correspondingto a negative phase difference. The two output lines are coupled throughcommutating gates. to be fully described undclj B. 118p. "8n. 218p. 218m418p.

\ 418m sequentially to each one of four local slave channels including.respectively. an adder-subtractor I19, 219, 319, 419 and a divider 120.220, 320, 420. The

. function of eachadder-subtractor. such as 119. is to ad- 1 just the2,040 KC reference.oscillatorsignal. from 114,

by either adding a pulse for each positive'pulse from generator 117. ordeleting a pulse for each negative pulse from generator 117. Thefollowing dividers 120,

120. 320, 420 convert the adjusted 2.040 KC signal to the 6.8 KC signalwhich is to be compared in phaseerror detector 116. Each pulse additionin addersubtractor "9 changes the phase of the 2.040 KC signal by 360.After division by a factor of 300 by divider 120, the net effect on the6.8 KC comparison signal is to make a phase change of g l .2 orl/30Q'cycle therein.

As the receiver is moved with relation to the trans-. tnitting'stations. the phase of the received signal changes, and the phase-of thelocal comparison signal must be changed to maintain coincidence. Thepulses which correct the phase of the local comparison signal serve as ameasure of change of phase. and therefore of receiver change of positionwith respect to the respective transmitting stations. By properlycomparing the number of positive and negative pulses produced inphase'tracking apair of transmitting stations, as will be hereinafterexplained with reference to frame C. it is possible to'determine wherethe receiver lies within the I lanes and centilanes (FIG. la) which arecharacteristic of the Omega navigationsystem. l. Phase-Error Detector116 (H6. 3)

Phase-error detector 116 compares the 6.8 KC input.

signal. derived in mixer ll2b from the transmitting station l02 KCsignals a,.b'. c. d. with the corrected 6.8 KC comparison signal fromthe appropriate local channel. as follows. Transistor Ola constitutesanemitter follower amplifier for the signal received at input i ll2b.

1 This signal is fed through the two diodes D and 02a,

connected in push-pull arrangement. through balanced f transformer Tiaand capacitor C3a. Transistor 02a .constitules an emitter followeramplifier for the reference signal from terminal i 121, which is fed asa singleended signal into both diodes Dla and 02a through thetransformercenter-tap. The diodes Dla and D2a act as gates controlled bythe reference signal. and operate to pass alternate'sectionsiof the 6.8KC input signal. Since each tracking loop orchannel is gated to correctphase every time its associated "transmitter signal is received(approximately. once every l0 seconds in conventional Omega practice).the phase detector 116 will make W 3 small corrections and operate nearzero output.

The signal passe'd by diodes Dla and D is integrated by capacitor C4a'to remove high-frequency AC components. and is then fed to anoperational inte grater including amplifier ARla having feedbackcomponerits R90. C54. Kilo-The operational integrater re duces the highfrequency components of the phaseerror signal andprovides sufficient DCgain to negate the effects of offsets caused by drift which isassociated with a bilateral pulse generator of the type describedfibelow.

The servo loop gain' is detemtined by the DC gain of the phase-errordetector and the time constaint of the bilateral pulse generator. Thisdesign provides 'a noisefree. phase-tracking velocity'of approximately3.6 microseconds per second or a bandwidth in this. instance of .036cycles. approximately. The performance of this n0isefree bandwidth.examined in an input signal to noise ratio of l/ l0 in a 100 Hzbandwidth. yields a 5 microsecond lagangle of a baseline velocity of 35knots. which is deemed adequate for current vehicle movementrequirements. The output of the phase-error detector 1 16 is a DCvoltage which is either positive. .neg ative or zero. and of variablemagnitude. depending on the phase relationship of the compared signals.The DC signal appears at terminal 0 117. 2. Bilateral Pulse-Generator117 (FIG. 4)

The DC output voltage from the phase-error detector H6 is. convertedinto a series of pulses whose frequency depends on the magnitude of theDCvoltage. Depending on the polarity of the DC voltage. the pulses aresegregated to output terminal 0 118a (negative polarity) or outputterminal 0 118p (positive polarity).

The DC input from terminal 1' 116 is integrated by operational amplifierARZa to produce a signal ramp whichwill be either positive or negative.depending on the polarity-bf the voltage. The steepness of the ramp isdetermined by the magnitude of the voltage. Across integrating amplifierARZa are connected two pairs of complementary transistors Q3a-Q4a andQSa-Q6a connected regeneratively to form an artificial fourlayer diode.When the voltage across either pair reaches the breakdown voltage. thepair conducts. dischargingthe integrating capacitor C9a. As a result. apositive or negative saw-tooth wave, whose polarity and frequency dependon the input voltage. is pro duced at the output of operationalamplifier AR-Za. The saw-tooth wave is differentiated by capacitor C 16ato produce a series of positive or negative pulses. These pulses areamplif ed through transistor 07a. and segregated by the pulse separatorformed by transistors 08a and 09a; Transistor 08a is biased to besensitive only between compared signals. The pulse frequency. in the tothe positive pulses which thus appear as positive pulses at outputterminal 0 "8n. Transistor Q is biased lobe sensitive only to negativepulses which are then inverted by transistor 0100 to appear as positivepulses at output terminal 0 "8,0; The frequency of the pulses depends onthe input voltage magnitude. which is dependent on the magnitude of thephase difference examples-shown. .is on the order of 0 tots!) cycles persecond.

': 3. input 5r shim Gates 118p. ll8u(FlG.' s)

As shown in FIG. 2. the phase-emu detector I16 and the bilateral pulsegenerator ll? serve all of the local trackitigchanitels, being connectedsequentially to the channels by input gates llflp and nan. etc. andoutput gates 12!. etc'l,flfhe irt'putgates ll8p. "8a are shown in FIG.5.,They are simultaneously gated by a signal at i to pass pulses fromthe bilateral pulse generator "710 the .adder-subtructor ll) and to theadd and,

subtract counter storage I25- and I26. Besides the shared detector "6and generator ll). each-docs! trackingchunnel has connected to thereference-deem viutor IE4 itsnwnseparatc udder subtractor ll). 2).

etc. and tracking synthcsirer I20. 220. etc. a construe tion of which is.(lE..l'll'VGCl in detail below for a single i .4.Adder s ubtractorllamas} at input 1' 8n.

channelt the other channels having identical compo nents.

The adder-subtractor "9 uses the pulses produced by bilateralpulse'generator 117 to adjust the phase of local 6.8 KC reference signalwhich is compared to the incoming signal in phase-error detector 116.The 'adder-subtractor 2119, accordingly. has inputs from the bilaterallpulse generator 117 (through gates. 118p; [118"), and it moreover hasan input 1' 114 from the 2,040 KC local reference oscillator 114, Theoutput at terminalo 120 is a 2.040 KC signal with'pulse additionscorresponding in number to pulsesat the input! 118p. and pulse deletionscorresponding in number to pulses at input i ll8n. This modified 2,040KC signal is then divided downwardlyby a factor of 300 in the trackingsynthesizer l20 to produce a phase-corrected 6.8 KC signal suitable forcomparison in the phase-error detector 116. t I

The operation of the adder-subtractor 119 is as follows. For simplicity.the add and subtract functions will be taken separately. A'n add pulsethrough gate 118p f triggers an Eccles-Jordan flip-flop 250, which opensgate Z6a. The opening of gate 26a permits the negarive-going portion ofthe 2,040 KC signal to trigger monostable multivibrator 28a to produce a100 nanosecond delay. At the conclusion of this l nanosecond I delay.monostable multivibrator 29ais triggered and produces a second 100nanosecond delay pulse which isadditively combined with the 2.040 KCsignal in gate 212a, .the 2,040 KC signal with inserted pulse thenpassing through gate 214a to output terminals 0 120. The signal whichstarts the first multivibrator 28a. also resets flip-flop ZSa throughgate 24a, to return the componentsto starting condition so that a secondadd pulse will produce the same result.

- Subtract pulses through gate ll8n trigger a separate flip-flop Z180which opens gate Zl7a to permit the i 2.040 KC signal to triggermonostable multivibrator a. Monostable multivibrator Z150 has a periodof approximately600 nanoseconds. which-is slightly greater than thelength of a single 2,040 KC cycle. This 600 nanoseconds pulse is thenused to inhibit gate 214a to interrupt the 2.040 KC pulse train for thislength of time, thereby eliminating one pulse. The pulse train. fwithdelection, appears at output 0 120. The pulse H. 1- fw hich triggersmultivibrators ZlSa alsoj'res'ets flip-flop '1 218a through'gate 219a sothat original conditions are again established "and the process canrepeat.

The signal at output terminal a 120 is thusa 2.040

I KC signal which has itsphase advanced 360 for each pulse at input 1'118p, and retarded 360 for each pulse reference signal inaddcn-subtractor l I). This phase corrected a8 KC traclting'signal ithen imm w through gate 121 to be compared in phase-error detector I16with the received signal from the" station trans mitting at the time.Duringthc time that a local tmcle m of the. coincidence V arebeingcorrected by the servo mechanism which has been described. Because ofthe discrete nature of the phase correction signal. the

, reference 6.8 KC signal moves back and forth across LII the zero-errorposition by steps of l.2. with the result that the actual RMS error isless by a factor-of'2. During the time that a tracking channel is gatedoi it of circuit with the received signal (9 out of every 10 seconds inordinary-Omega practice), the 6.8 KC comparison signal continues at thephase last established. The pulses produced by the, bilateral pulsegenerator 117 are then interpreted as incremental changes of position ofthe receiver with respect to any one transmitter. By combining pulsesfrom two tracking channels, it is possible to interpret the pulses aschanges of position within the hyperbolic lanes of phase coincidencebetween the signals of the two transmitters so tracked. Since 300 pulsesof one sense i-or would result in complte'phase change of onecycle ofthe local 6.8

tracking signal. it follows that each single pulse represents 1/300 of alane.

The numerals l to 20 in FIGS; 3 to 5 represent in conventional mannerthe terminal numbers of the respective integrated circuit devices towhich they are applied. The-numerals 0 and l within the flip-flopsymbols indicate the output states in conventional manner.

The nature and electrical connections of the elements of each of thecircuit components contained in frame A (with the exception of. theconventional counter at 120) are clearly shown in FIGS. 3 to 5.

B. Commutator Circuitry Selection ofxthe appropriate channel (H9, 120 to419, 420) is carried out by means of eight input gates 113p, 11811 to418p. 4l8n and four output gates 12] to 421 in response to a gatingpattern signal generated by timing function generator 115. Generator M5produces a gate pattern which is synchronized with the in- 1 comingOmega envelope pattern by slewing circuitry comprising a manuallycontrolled pulse generator 124 which. by manual selection, providespulses to be 7 added or subtracted in a synchronizing circuit 122. The

synchronizing circuitlZZ operates similarly to the addclock signalderived fromthe local reference oscillator 114. The clock signal. withits phase advanced or rctarded for synchronization. operates shiftregisters in the timing function generator 115, which in turn controlsthe opening and closing of input gates 118p. 118:: to 418p, 4181';(jllustratedin FIG. 5) and output gates E2] to 421 (illustrated in FIG.6).

In addition to providing a gating signal to co mmutate the localtracking'channels. the timing function genertv ing at it ill Hr. rate.and a shift register FIG. 7) which 5 gates ll9p. H891 to am 418" gates[21 to 421. (Fit). 6).

ing channel is gated into the phase detecting circuit. cr-- provide longand short. gates used to open and close Pulses from the-decade divider(Fltfliz'ti) are fed at u l0 Ha rate to a ll! of FIG. 0a. the basic timequintet FIG. Stand output a zero pulse corresponding to the initiationof the internally generated Omega timing cycle. i.e. one pulse isgenerated for each 10 second interval.

. The binary outputs are also combined thru several gates and collectedin Z18 to generate eight pulses durihg the 10 second interval. each oneoccuring at a time corresponding to the end of the short gate interval.

These pulses at 0200 (FIG. 6a'lare fed to the sampling ;counter anddecoder (FIG. 6b) to i 200. The output of 23d sets binary Z6 to enablegate Zlc. Zl0c and 210!) passthe Hi. pulse train which appears an 115into .24, Z8 and Z12, a three-stage binary counter. These stages countat a l0 Hz rate until a digital six" is gen erated in 23!) which putsout a pulse actuating 21, a

- one shot multivibrator whose output resets binaries Z4, Z8 and 212 tothe zero state and in addition resets 26,

thereby inhibiting Zl0c and stopping the IQ Hz input until the nextpulse occurs at i 115. Outputs :from the binary counters are combined in27g and 23a for a digital number corresponding to a *one" and a -five"rcspectively which set and reset binary Z2. The output of binary 22corresponds timewise to the short gate signals previously mentioned.

Outputs from the binary counters are further combined in 27c for abinary number three. This three is combined with the 10 Hz clock in 210ato provide a synchronous pulse at the eitact time to initiate the longgates previously mentioned. This pulse line is fed out throughZlOd toconnection 0202 to the long-gate shiftregister (FIG. 6b). Other digitalnumbers are decoded in-Zl3a. 213b, Zllb, Zllc and Zlla. Two of theseare" combined with long gates from the long gate shift register fed inon 214b, pin i 203 and 214a, pin i 204 to generate discrete pulsesbetween the third and fourth Omega transmission'segments which are usedalong with the Zero pulse previously mentioned to initiate count outoperation in 1258: 126, 225 & 226, and 325 and 326 of FIG. 2 at discreteintervals during the 10 second timing cycle. 'A reset pulsecorresponding to the zero pulse generrated in the: basic time counterand decoder feeds the longgate shift register (FIG. 6b.) and resets theshift register comprising Z8, Z4, Z3, Z7, Z6, Z2, Z1, and Z5, once everyl0 second interval. The drive pulse, corresponding to the binary 3described in the sampling counter and decoder shifts the register onestage for each input. thereby generating a pulse on each of the eightbuffered output lines provided by 212b, 212d. 21 lb, Z151, 215d, Zl4c.214d and Z1 la in proper time sequence. These pulses are the long gatesreferred to earlier. I I r The output of each stage of the shiftregister is in addition fed to gates 212e, 2110, Zl5b. 210b, Zl0c,

2141;, 29b, and 2%. During each long gate signahthesc gates are enabledand act to separate the short gate signals heretofore developed on oneline as described in tlie sampling counter and decoder and to provideseparateshcrt gate outputs as required to operate gates 12] to 421 (FIG.6). 2. Pulse Generator I24 (FIG. 6)

Pulse generator 124 is a conventional relaxation oscillator employing aunijunction transistor 0th. The

. l2 pulse generator 124 operates only when switch Slb is closedmanually to bias the circuit intooscillation.

By means of switch 52b, the output of pulse: generator 124 can beconnected either to time-advancing input i 124p or to time-retardinginput i l24n of the synchronizing circuit 124;

3. Synchronizing Circuit 122 (HO. 6)

Synchronizing circuit l22 has an input l 1143 which accepts a 17 KCreference signal derived from the local oscillator-114. This l7 KCsignal is divided by no in divider 122d to produce a pulse train of l00pps which, as modified in a manner now to be explained. appears atoutput terminal 0 "5 to run the shift registers in the timing functiongenerator 115. The I00 pps pulse train and the resulting gate pattern isslowed down" or hurried up" by the addition or deletion of pulses frompulse generator 124 which pulses are manually selected to be appliedeither to the time advancing input i 124p or the time-retarding input il24n. A pulse appearing at input i 124;: is treated as follows:

A pulse appearing at 124p sets flipflops 28b enabling flip-flop Z1017thru gates which are enabled by either Z4b or Zl5b. The next lOO ppssignal occurring at the output ofZlb operates to setflip-flop 21%. Theoutput of Z101) enables gate 26b to pass one pps-pulse to initiate twodelay one-shot multiocrotors Zl8b and 21912. The output of Z1912 isdelayed by Zl8b until approximately midway between the first and secondsequential I00 pps outputs from Zlb at which time it generates a narrowpulse which is inserted in the 100 pps trainby action of gate 22b.

The change in state of flip-flop 21% is led to set flipflop 2% whichinhibits gate 25b through gates 24b or 215]). The second sequential lOOpps output from Alb resets Zl0b to its original state inhibiting gate26b and returning the circuit to rest until the next pulse on line c124p changes the state of l'lip-ilopZSb.

Similarly, a pulse appearing at the retard input i l24n is treated asfollows:

A pulse appearing at 124a sets flipflop Z l Zb. thus enabling flip-flop21,4!) thru gates 2176. which is in turn enabled by either gate 21 lb orZl6b. The next following 100 pps at the output of 22b sets flip-flop21%. thereby inhibiting gate 23!), and changing the state of Z20!) toinhibit gate 2176 thru either gate 21 l6 or gate Zl6b. The secondsequential 100 pps pulse at the output of 22!) resets Zl l6 whichenables gate 23]) and the circuit is at rest condition. having deletedone pulse in the I00 pps train appearing at the output of gate 23b.

foregoing synchronization circuit. This circuit essentially serves tophase shift the Ill-second cycle of the timing function generatorsgating pattern. relative to the time bPlSt." established by thereference oscillator 114. This is accomplished by inserting extra pulsesin. or deleting some of the normal pulses from. the I 00 pps trainderived from the reference oscillator ll-tSince the reference oscillatorH4 is phase-locked to one of the received Omega signals (see descriptionof frame E below). the gating pattern can be made to coincide. withinl/lut) or a second. to the Omega signal pattern as received.

Synchronism can t e'ohservetl and verified with uscitloscope l3? i-Ki.Mrl'he oscilloscope [33 provides a I [Counter-storage I25 (FIG. 8)

trace for comparison purposes. i.e.. one trace being provided by theenvelope of the received Omega signal (developed inenvelope detector132) and the othentrace being provided by the gate pattern of the timingfunction generator 115, which also provides the sweep. By comparing thetwo traces visual observation of synchronism is possible. Other meansfor observing and verifying synchronization are available: For example.a pair of lights energized respectively by the gating pattern and by thereceived Omega signal envelope will show synchronization. Or. by way ofanother example.

. a meter comparing one channel's envelope with the A inthe localtrackingchannels provide the information usedby the circuitry of frame Cfora numberical readout of position in terms of lanes andcentilanes.pulses are stored in a counter-register as they are generated. and thenperiodically transferred to the felectro-mechanical counters 127.5,227.5 or 327.5.

Each electro-mechanical counter is adapted to display decimally theposition of the receiver expressed in '7' lanes and centilanes. inrelation to a pair of transmitting stations. Usual Omega practiceassigns a number to each of the hyperbolic lines of phase coincidencebetween a pair of transmitting stations and identifies the interlineregions as lanes. A centilan'e is. accordingly.

f. T a distance equal to one hundredth of the distance between the twolines which the receiver identifies After the lane and the centilanecount is initially set into one of the electromechanical counters. suchas 127.5. a

"charigeofposition of the receiver. producing phasecorre'ctive pulses ingenerator 117, is indicated in the following manner. Forsimplicity.therc will be de- 4 scribed only thecircuitry necessary forhandling two transmitting stations, such as 10a. 10b (FIGS. l, l a)which'comprises counter-storage 12S and 126., comparator and driver.127. and electromechanical counter 127.5. Circuitry identical to thatof127.5 is associated with counters 227.5 and 327.5. which may. forexample; display position with respect to transmitting stations 10b. lcand c. 10d, respectively.

Operation of the circuitry blocks I25, 126 and 127 is more easilyunderstood by first considering the arithmetic operations to be.performedtherein. Briefly.

bloclt. l2 5 adds pulses representing positive phase I chring es'in onechannel to pulses representing negative changes in a second channel.Block 126 adds pulses representing negative phase change in the onechanncl to' pulsesrepresenting positive phase change in the secondchannel. The pulse total of block l25 is applied to theelectromechanical counter 127.5 in a 'rense opposite to the pulse totalfrom block 126 to obtain the'difl'erence between the two numbers oftotal 5 pulsesfifhis difference represents. in'pulse terms normalizcd toccntilanes. the net change of phase at the re ceiver of the one channel:transmitting station. with respect to the second chanel's transmittingstation.

The storage circuit 125 of FIG. 8 has inputs i 118;; and i 218:: fromthe respective short gates. pulses from which are added in gate Zlc. Thepulses from the two inputs never-coincide to. give a false count. sincethe gates 118p and 2l8n. associated with different channels, are openedsequentially and never-simultaneously. As noted above. each pulseinserted or deleted to correct phase represents l/300-of a cycle ofphase change. To obtain a signal whose pulses each' represent onecentilane. the input pulses are therefore divided by three in thecircuit formed by 220 and 23c. These pulses in turn are applied to abinary count-up register formed by elements 240. 25c, Z6cand 270. whichregister has a counting capacity of 16.

The storage circuit 125 further. has an input i 222 from thesynchronizing circuit 122, as mentioned above, which feeds its 100 ppspulse train to a transfer pulse generator 115!) and a clock pulsegenerator 1155a.

both of which are actually part of timingfpnction generator 115 referredto abovea'l'he-transfer pullse generator [15b delivers a pulse to thepairs of storage circuits 125, 126; 225. 226; 325, 326 to instigate thereadout process. The pulses are delivered to the pair in sequence toreduce the power requirements of the receiver. but they are sentsimultaneously to both storage circuits forming'one pair, such as 125,126. The clock pulse generator-115a divides the 100 ppssignal by l0 toproduce a 10 pps clock-pulse train.

When a transfer pulse is delivered to the storage circu it 125, it opensgates 29c through 216C to transfer the count in thecount-up register toa second register comprised of Z190 through Z220. As the circuitconnections show, the tranfer is of the conjugate of the number ofaccumulated pulses in the count-up register. For example. if thecount-up register contained the binary number 001 l. this would betransferred as is conjugatc l 100 to the count-down registerv Thetransfer pulse. in addition to causing the conjugate transfer of thestored-up number of pulses. also triggers a delay component Z25c whichresets the count-up register to 0000 to begin counting anew.

The transfer pulse furthermorelatches Z23c into a state enabling gateZl8c to pass to the countdown register the 5 pps signal derived bydividing the i0 pps clock signal from liSa'in binary 2170. The 5 ppssignal through gate Zl8c at 0-127 Passes-to comparator and coil driveroutputl27 (FIG. 9)'and also is applied to; the count-down register. Whenenough pulses have been applied to the count-down register to increasethe count (from the transferred conjugate value) to i l l l. the gateZ24c is activated and unlatched to disable Zi8c so that no more pulsesm'll to the comparator and coil driver [27 until the next transfer pulsefrom 5b is applied.

From the foregoing it is readily seenthat the storage and count-outcircuit functions broadly as follows. The input pulses are divided bythreeahd stored in a count-up register until a transfer pulse causes thecount to be transferred its conjugate to a count-down register. Thecount-up register is immediately reset so that it will keep countingpulses generated in M7. The transfer pulse also enables a clock'pulsctrain to dcplate the countdown register. at the end of which thecircuitry is reset to its initial condition;

FIG. 9 is a timing diagrnmtlepicting certain wave forms during a typical\0 second interval ofoperation of storage and count-out l25. l llllfh.circuit. The dia-

1. A navigation system for fixing the location of a vehicle, of the typewherein pairs of transmitters are employed to determine lanes ofposition defined by phase angle differences of signals from thetransmitters, comprising: a plurality of synchronously operated signaltransmitters producing sequentially transmitted, pulsed signals; firstmeans for receiving said signals from said plurality of transmitters,including signal-pulse generator means for producing a local signalrelated to said sequentially transmitted signals; means associated withsaid first means for detecting consecutive sequences of said transmittedsignals, respectively, and for separately comparing their respectivephase angles with the phAse angle of said local signal; second means formatching the phase angle of said local signal with the phase angles ofthe respective transmitted signals during said sequences, said secondmeans including means for converting phase angle differences between thetransmitted signals received by the first means and said local signalinto a number of discrete pulses generated during the presence of saidphase angle differences and for indicating, from the number of saiddiscrete pulses, the magnitude of the respective phase angledifferences; and means for correlating said phase angle differences toindicate the position of said vehicle.
 2. The system according to claim1 wherein the transmitted signals and the locally produced local signalare digitally coded, pulsed signals.
 3. The system according to claim 2wherein said phase angle differences define time intervals between therespective signals.
 4. The system according to claim 2 wherein saidsecond means includes means for inserting and deleting thephase-difference-defining pulses into and from said local signal,respectively, depending on the sense of the phase difference.
 5. Thesystem according to claim 2 wherein said phase-difference-defining meansgenerates pulses at a first point whenever phase difference is of onesense, and at a second point whenever phase difference is of the othersense.
 6. The system according to claim 5 wherein said second meansincludes third means for inserting pulses at said first point into saidlocal signal, and deleting means for deleting pulses at said secondpoint from said local signal.
 7. The system according to claim 6 whereinsaid third means includes an input for said phase-difference-definingpulses, and fourth means responsive thereto and to said local signal forinterpolating between two successive pulses of said local signal andadditional pulse for each phase-difference-defining pulse appearing atsaid output.
 8. The system according to claim 7 wherein said fourthmeans includes a first monostable multivibrator placed in triggerablecondition by a phase-difference-defining pulse and triggered by thefirst subsequent local signal pulse, the period of said first monostablemultivibrator being less than the interval between successive localsignal pulses, and a second monostable multivibrator triggered by saidfirst monostable multivibrator to produce additional pulses, and meansfor combining said additional pulses with said local signal pulse train.9. The system according to claim 6 wherein said deleting means includesan input for said phase-difference-defining pulses appearing at saidsecond point and fifth means responsive to saidphase-difference-defining pulses and to said local signal pulses forblocking one pulse from the local signal pulse train each time aphase-difference-defining pulse appears at said input.
 10. The systemaccording to claim 9 wherein said fifth means includes a monostablemultivibrator placed into triggerable condition by aphase-difference-defining pulse and triggered by the first subsequentlocal signal pulse and a gate inhibited by said monostable multivibratorfor a period sufficient to block a single local signal pulse.
 11. Thesystem according to claim 6 further comprising means for frequencydividing said local signal with insertions or deletions, to obtain aphase-adjusted comparison signal of the same frequency as saidtransmitted signal.
 12. The system according to claim 11 wherein saidsecond means further includes phase-detector means for comparing thephases of said transmitted signals and said comparison signal, saidphase-difference-defining means being responsive to said phase-detectormeans, thereby to lock the phase of the comparison signal to the phaseof the selected sequence of the transmitted signals.
 13. The systemaccording to claim 5 wherein said phase-difference-defining meanscomprises an input, a sawtooth-wave, signal generator which has itsoutput frequency controlled by tHe magnitude of a control voltage atsaid input, and the polarity of the output sawtooth-wave controlled bythe polarity of said control voltage, differentiator means for saidoutput sawtooth-wave signal for producing pulses of correspondingfrequency and polarity, and separating means for directing pulses of onepolarity to said first location and pulses of the other polarity to thesecond location.
 14. The system according to claim 13 wherein saidseparating means comprises a first amplifier biased to respond only topulses of said one polarity and having its output at said firstlocation, and a second amplifier biased to respond only to pulses ofsaid other polarity and having its output at said second location. 15.The system according to claim 13 wherein said matching means comprisesphase-detector means with an output voltage of magnitude correspondingto the magnitude of the phase difference and of a polarity correspondingto the sense of the phase difference, said phase-detector output voltagebeing applied to the input of said phase-difference defining means. 16.The system according to claim 1 wherein said local signal has afrequency which is an integral multiple of the frequency of thetransmitted signals applied to said matching means, and wherein saidmatching means comprises means for inserting and deleting saidphase-difference-defining pulses into and from said local signal,respectively, depending on the sense of the phase difference; and meansfor frequency dividing said local signal with insertions and deletionsby said integral multiple, thereby to obtain a phase-adjusted signal atthe transmitted signal frequency to compare therewith for phasedifference, thereby providing a phase-adjusted comparison signal. 17.The system according to claim 16 wherein said second means furtherincludes phase-detector means responsive to the phase difference betweensaid phase-adjusted comparison signal and said transmitted signal, andwherein said phase-difference-defining means is responsive to saidphase-detector means.
 18. The system according to claim 1 wherein saidmeans for detecting consecutive sequences of said transmitted impulsescomprises a timing-function generator, and gate means for connectingsaid second means into phase-matching relationship in response tosignals from said timing-function generator.
 19. The system according toclaim 18 wherein said timing-function generator producesgate-controlling signals from an input clock-pulse signal, and saidselecting means further comprises means for synchronizing saidgate-controlling signals with said consecutive sequences of transmittedsignals.
 20. The system according to claim 19 wherein said synchronizingmeans comprises a pulse generator and means for selectively inserting ordeleting pulses therefrom into or from the clock-pulse signal operatingthe timing-function generator, thereby to advance or retard,respectively, the gate-controlling signal.
 21. The system according toclaim 20 wherein said means for selectively inserting or deleting pulsescomprises a first input, means responsive to pulses at said first inputfor inserting pulses into the clock-pulse signal, a second input, meansresponsive to pulses at said second input for deleting pulses from saidclock-pulse signal, and manual switch means for connecting said pulsegenerator to one of said first and second inputs.
 22. The systemaccording to claim 18 wherein said second means comprises a plurality ofmeans for combining said phase-difference-defining pulses with saidlocal signal, and wherein said gate means connect said combining meansto said phase-difference-defining means.
 23. The system according toclaim 22 wherein said timing-function generator produces a pattern ofgate-controlling signals from a clock pulse train, and wherein saidselecting means comprises synchronizing means for advancing andretarding said pattern to cause said consecutive sequences oftransmitted impulses to be contemporaneous with The connection ofselected ones of said plurality of combining means, to saidphase-difference-defining means, thereby to associate each sequence oftransmitted signals with a single combining means.
 24. The systemaccording to claim 23 wherein said synchronizing means comprises a pulsegenerator, and means for selectively inserting or deleting pulsestherefrom into or from the clock pulse train operating the time functiongenerator, thereby to advance or retard, respectively, thegate-controlling signal.
 25. The system according to claim 1 whereinsaid correlating means, for phase-difference-defining pulses generatedfor a pair of transmitting stations, comprises: means for counting thenumber of pulses generated, numerical display means, and means forchanging the indication of said numerical display means in accordancewith the number of pulses generated.
 26. The system according to claim25 wherein, for each transmitting station, saidphase-difference-defining pulses are generated at a first location forone sense of phase difference and at a second location for the othersense of phase difference and wherein said counting means comprises afirst partial sum means for counting together pulses appearing at thefirst station''s first location and the second station''s secondlocation; a second partial sum means for counting together pulsesappearing at the first station''s second location and the secondstation''s first location, and means for combining the counts of saidfirst and second partial sum means to produce a number of pulses equalto the difference therebetween for application to the indicationchanging means.
 27. The system according to claim 26 wherein each ofsaid partial sum means comprises means for storing the accumulated countand means for periodically transferring the count, and resetting saidstoring means to an empty condition.
 28. The system according to claim27 wherein said count is periodically transferred to a register which isdepleted by a clock pulse signal, and wherein gate means pass said clockpulse signal, between the times of transfer and full depletion, to saidcombining means.
 29. The system according to claim 27 wherein said firstand second partial sum means each periodically emit a number of countoutpulses equal to their accumulated count, and wherein said combiningmeans comprises first gate means for passing countout pulses from thefirst partial sum means and second gate means for passing countoutpulses from the second partial sum means, said gates each beinginhibited by countout pulses appearing at the opposite gate, thereby toblock simultaneous countout pulses and to pass only countout pulsesrepresenting the difference between their respective numbers.
 30. Thesystem according to claim 29 wherein said numerical display meanscomprises an electromagnetic counter having a coil for increasing thecount and a coil for decreasing the count, said coils being responsiverespectively to countout pulses passed by said first and second gatemeans, whereby said combining means prevents said coils from respondingsimultaneously.
 31. The system according to claim 1 wherein saidcorrelating means includes chart recorder means for indicating theposition of said first means.
 32. The system according to claim 31wherein said second means includes means for inserting and deleting saidphase-difference-defining pulses into and from said local signal duringsaid sequences, and independent means for dividing the generator pulseswith insertions and deletions to produce for each sequence a comparisonsignal with a phase adjustment, and wherein said correlating meanscomprises phase-detector means for comparing a pair of said comparisonsignals and said chart recorder means is responsive to saidphase-detector means for indicating the position of the first means withrespect to the transmitters corresponding to a respective pair ofcomparison signals.
 33. The system according to claim 1 wherein saidfirst mEans includes an antenna and means for amplifying and filteringthe antenna output characterized in that said amplifying and filteringmeans includes limiting means and said amplifying, filtering, andlimiting functions are distributed successively in each of a pluralityof stages, thereby to minimize phase shift.
 34. The system according toclaim 33 wherein said amplifying, filtering, and limiting means arecorrelated so that said transmitted signals are limited at an earlierstage than undesired signals outside the filter bandwidth.